The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device, which can prevent the decrease of the width of an active region.
With the development of semiconductor manufacturing technologies, semiconductor devices are becoming more highly integrated and accordingly, the size of cell transistors are gradually decreasing. As the size of cell transistors decrease, the size of an isolation structure for electrically isolating devices also decreases.
As a result, techniques for effectively forming a small sized isolation structure have been examined in order to raise the integration level of a semiconductor device. That is to say, as the area of the semiconductor device occupied by the isolation structure decreases, techniques for forming an isolation structure capable of maximizing an insulation effect between elements have become increasingly important.
Hereinafter, a method for forming the isolation structure of a semiconductor device according to the conventional art will be schematically described with reference to FIGS. 1A and 1B.
Referring to FIG. 1A, a hard mask composed of a pad oxide layer 111 and a pad nitride layer 112 is formed on a semiconductor substrate 100 such that the isolation regions of the semiconductor substrate 100 are exposed.
By etching the exposed portions of the semiconductor substrate 100 using the hard mask as an etch mask, trenches 113 are defined in the isolation regions of the semiconductor substrate 100. A sidewall oxide 114, a linear nitride layer 115, and a linear oxide layer 116 are sequentially formed on the surfaces of the trenches 113.
Referring to FIG. 1B, an insulation layer 115 for isolation is filled in the trenches 113 which are formed with the linear oxide layer 116. The isolation structure 123 of the semiconductor device is formed by CMPing (chemically and mechanically polishing) the insulation layer for isolation. The isolation structure 123 is formed higher than the active regions 110 of the semiconductor substrate 100.
However, the isolation structure 123 formed according to the conventional art is likely to be gradually lost in a subsequent cleaning process. As a result, the isolation structure 123 has a height, which is lower than that of the active regions 110 of the semiconductor substrate 100.
FIG. 2 is a view illustrating a state in which an isolation structure is lost by implementing a cleaning process.
Referring to FIG. 2, as the isolation structure 123 has a height that is lower than that of the active regions 110 of the semiconductor substrate, a phenomenon, i.e., a moat phenomenon, occurs in which portions of the isolation structure 123 are depressed around the active regions 110. The moat phenomenon causes the oxidation of the sidewalls of the active regions 110 during an oxidation process for forming a gate oxide layer and thereby decreases the width of the active regions 110.
FIG. 3 is a view illustrating a state in which the width of the active region of a semiconductor substrate has decreased.
Referring to FIG. 3, the phenomenon, in which the width of the active regions 110 decreases by a gate oxidation process, serves as a factor that increases the resistance of the semiconductor device.
Meanwhile, after the isolation structure 123 is formed, an SEG (silicon epitaxial growth) process for forming an epi-silicon layer on the active regions 110 is implemented.
FIGS. 4 and 5 are views illustrating states in which epi-silicon layers are formed by an SEG process according to the conventional art.
Referring to FIG. 4, where the SEG process is implemented with the active regions 110 having a narrow width, the epi-silicon layer 160 can be formed into an abnormal shape.
Referring to FIG. 5, where the SEG process is implemented with the active regions 110 having a narrow width, a bridge phenomenon can occur between the epi-silicon layers 160.